As manufacturers strive to meet currents demands for semiconductor device performance, the interfaces between layers or components within the devices are becoming increasingly important and are currently inhibiting the optimization of device performance.
One example of such an interface is that between the source and drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the contacts formed to make electrical connections to them. Using conventional methods, the contact resistance between the source/drain and the contact is more than 1×10−10 nΩ-cm2, which may be detrimental to the performance of advanced complimentary metal-oxide semiconductor (CMOS) device. Another example is the interface between the semiconductor substrate and the gate stack in transistors formed on “III-V” (e.g., gallium arsenide) and germanium substrates. Typically, the interface trap density (Dit) at these interfaces is greater than 1×1011 cm2/eV, which hinders the performance of such devices.